Error handling verification of serial communication designs

Some of the following concepts related to error handling verification are generic across the design type but the focus of this blog would be on the functional verification of error handling in protocol based serial communication designs.

Error handling verification is a complex, effort intensive and has potential to throw the schedule off the track. To add to problem the effort invested can turn out to be low returns on the investment.

If it’s not well thought out, error-handling verification can soon turn into a nightmare. Other feature verification also has chances of going wrong but error-handling verification has very high probability of going wrong. It’s a slippery slope, which leads to quicksand. Caution has to be exercised while planning.

Typical verification environment for serial interface based designs looks as following:

Error handling in hardware is verified through the

• Error injections on transmit (Tx) side of the bus functional model
• Error injection on receive (Rx) side of the bus functional model
  • Behaving as if the error has been detected on receive side of the bus functional model
• Checking response from the DUT on receive (Rx) side bus functional model.
  • Checking can also be done as part of the monitor which is separate component or built in to the Bus functional model itself

Error injection verification needs a good planning from multiple points of view. They are following:

1. Error injection scenario enumeration thought process
2. Definition of the sensible error handling verification plan
3. Error injection capabilities of bus functional models
4. Error injection implementation in bus function models
5. Structuring the error injection tests
6. Execution and Closure of the error injection verification