Testbench architecture – Application world abstraction
Application is the reason for existence of the DUT. Application is combination of the software and hardware. Hardware may be design under test combined with…
Testbench architecture – Layered view
Layered view of test bench is grouping of the related functionality components into five layers. In the following article let’s look at what these…
Design under test (DUT) for Verification Engineer
Understanding design under test (DUT) is very important for verification engineers. Remember RTL design gets taped out as final ASIC product. Sales of this product brings…
Effective randomization in Constrained Random Verification
One of the key component of coverage driven constraint random verification environment is randomization. High-level verification languages provide various constructs to implement the randomization. However…
How to improve UVM use effectiveness?
UVM is primarily based on a framework reuse model. Effective use of Universal verification methodology (UVM) requires understanding of effective framework reuse requirements. Effective framework reuse requires…
Verification quality improvement – Test bench
Test bench quality overhaul involves three primary activities cleaning, trimming and refactoring. First step of quality overhaul is cleaning and trimming. Typically verification solutions with…
Testbench quality improvement: Refactoring test bench
First step in refactoring the test bench code is to identify the code requiring refactoring. Poor code in the test bench typically bloated, showing the…
Testbench quality improvement: Refactoring tests
First step to refactoring tests is to review tests to identify the possible reductions. Reduce the number of tests to provide the necessary coverage. This is…
Testbench quality improvement: Cleaning test bench
First step in the test bench quality rehaul is cleaning the test bench code. Clean compile and run time warnings Review the compile warnings from…
Verification quality improvement – Regression & Debug
Regression phase is the climax of the functional verification. This is phase during while the real value of the functional verification is being realized. That’s…