According to wikipedia Pentium FDIV bug affects the floating point unit(FPU) of the early intel Pentium processors. Because of this bug incorrect floating point results were returned. In December 1994, Intel recalled defective processors. In January 1995, Intel announced “a pre-tax charge of 475 Million against earnings. Total cost associated with the replacements of the flawed processors.

What went wrong here?

According byte.com web page archive, Intel wanted to boost the execution of their floating-point unit. To do that they moved from its traditional shift-and-subtract division algorithm to new method called SRT algorithm. SRT algorithm uses a lookup table. Pentium’s SRT lookup table implementation is matrix of 2048 cells. Only 1066 of these cells actually contained the valid values. Due to issue in script loading the lookup table 5/1066 entries were not programmed with valid values.

SRT algorithm is recursive. This bug leads to corruption only with certain pairs of divisors and numerators. The “buggy pairs” are identified. They always lead to corruption. At its worst, the error can rise as high as the fourth significant digit of decimal number. Chances of this happening randomly, is about 1 in 360 billion. Usually the error appears around the 9^th or 10^th decimal digit. The chances of this happening randomly, is about 1 in 9 billion.

Isn’t randomization on inputs sufficient?

Here you can see even if we had constrained random generation on divisor and numerators how low is probability of hitting the buggy pair. Even if we create the functional coverage on the inputs how low is probability that we would specifically write coverpoints for the buggy pair.

Of-course now we have formal methods to prove correctness of such computationally intensive blocks.

We are already convinced that constrained random hitting on this buggy pair has very low probability. Hence even if it hits this case it may take long wall clock time. Pure floating-point arithmetic verification approach alone is not sufficient.

For a moment if you think what could have helped maximize the probability of finding this issue in traditional simulation based verification?

Simulation world is always time limited. We cannot do exhaustive verification of everything. Even a simple 32-bit counter exhaustive verification would mean 2 ^ 32 = 4G of state space. That’s where the judgment of the verification engineers plays major role as to what to abstract and what to focus.

Story of curious engineer

Let’s say a curious verification engineer like you looked inside the implementation. He tried to identify the major blocks of design and spotted the lookup table. His mind suddenly flashed insight floating-point inputs must use all valid entries of the lookup table. This is one more critical dimension for the quality of the input stimulus.

Let’s say he thought of checking that by writing functional coverage on input address of the lookup table. He thought of adding a bin per each valid cell of matrix.

This could have helped maximize the probability of catching this issue. There is a notion that verification engineers should not look into design as it can bias their thinking. While the intent is good but let’s not forget we are verifying this specific implementation of requirements. Some level of balancing act is required. It cannot be applied in purity.

He scans the following lookup table organization. Thanks to david deley for providing it:

Lookup table organization

Our curious engineer quickly makes notes about the following facts about the Look up table:

The matrix is organized as 128×16 = 2048 cells.
Out of these only 1066 cells are used
His well trained eyes notices that table is slightly asymmetrical
There are total of
- 20 rows at the top that have varying level of cell usage
- 46 rows that use all the cells of row
- 20 rows at bottom that have varying level of cell usage

He decides functional coverage on access for all the valid cells and simple assertion to check if the values were one of the {-2, -1, 1, 2}. Well assertion is simple enough in this case.

But the functional coverage requires 1066 bins. Due to asymmetrical nature it would at least need 86 entries of varying ranges to be coded. Any small change in the lookup table he would need to repeat it again.

Now remember although our engineer is curious he also has packed schedule to code the stimulus and write checks. Effort to write functional coverage is certainly discouraging. So he drops writing functional coverage and we all know what happened.

What could have helped this curious engineer?

Certainly it’s a daunting task to satisfy the curiosity of verification engineers. Not if the functional coverage is made more programmable. What if he had access to use the python along with the SystemVerilog functional coverage?

What would he have said? He would have said “easy peasy lemon squeezy”

Store all the valid row addresses in dictionary as keys
Store the mask of valid column address as values
- For example the first row address “0101.011” would contain the mask of “0000_0000_0000_0001”
Use two loops one looping over the row address and another looping over valid column address to create the bins
This also leads to highly programmable approach making any future changes quite easier

Here is how the code would look like:

Input: Python
Output1: Functional Coverage

#!/home/utils/Python-2.7.5/bin/python
########################################################################################
# 
#  Title: Lookup table address coverage  
#  Description:
#  For look up table organized as matrix with varying number of cells usage in
#  each row, creates the covergroup with the bin per cell
#  Step 1: Store the valid row addresses bits only as key of dictionary
#  Step 2: Store the mask indicating the valid cells with 1 as values in dictionary
#  Step 3: Loop through row and column address to create bins for each cell   
#  Category: EKB 
#  Status: PUBLISH 
#
########################################################################################

from curiosity_user_common_utils import *
from numpy import binary_repr

# Extends fro the "curiosity_user_lib" which has built in functions to ease the creation of the wb_input entries
class curiosity_dut_lib(curiosity_user_lib):

    def set_dut_spec(self, **dut_spec_dict):
         self.dut_spec =  copy.deepcopy(dut_spec_dict)
    
         # Set default value for all entries
         self.set_default_value_wbv_entry(
            WBV_CLOCK = self.dut_spec['__DUT_CLK__'], 
            WBV_RESET = self.dut_spec['__DUT_RSTN__'],
            WBV_USR_META_VAR2VAL = self.dut_spec,
            WBV_LOOP_LIST        = [''],)

    def get_valid_cell_addr_bins(self):

       # Key : row address; Value: Mask representing valid cells matching LUT map shown in picture 
       lut_valid_entries_cell_mask = {
         # Top Half - 20 valid entries of varying valid elements
         '0101.011' : '0000_0000_0000_0001', 
         '0101.010' : '0000_0000_0000_0011', 
         '0101.001' : '0000_0000_0000_0011', 
         '0101.000' : '0000_0000_0000_0111',
       
         '0100.111' : '0000_0000_0000_1111', 
         '0100.110' : '0000_0000_0001_1111', 
         '0100.101' : '0000_0000_0001_1111', 
         '0100.100' : '0000_0000_0011_1111', 
         '0100.011' : '0000_0000_0111_1111', 
         '0100.010' : '0000_0000_0111_1111', 
         '0100.001' : '0000_0000_1111_1111', 
         '0100.000' : '0000_0001_1111_1111', 
       
         '0011.111' : '0000_0011_1111_1111', 
         '0011.110' : '0000_0111_1111_1111', 
         '0011.101' : '0000_0111_1111_1111', 
         '0011.100' : '0000_1111_1111_1111', 
         '0011.011' : '0001_1111_1111_1111', 
         '0011.010' : '0011_1111_1111_1111', 
         '0011.001' : '0011_1111_1111_1111', 
         '0011.000' : '0111_1111_1111_1111', 
       
         # Middle 46 entries of all cells valid
         '0010.111' : '1111_1111_1111_1111', 
         '0010.110' : '1111_1111_1111_1111', 
         '0010.101' : '1111_1111_1111_1111', 
         '0010.100' : '1111_1111_1111_1111', 
         '0010.011' : '1111_1111_1111_1111', 
         '0010.010' : '1111_1111_1111_1111', 
         '0010.001' : '1111_1111_1111_1111', 
         '0010.000' : '1111_1111_1111_1111', 
       
         '0001.111' : '1111_1111_1111_1111', 
         '0001.110' : '1111_1111_1111_1111', 
         '0001.101' : '1111_1111_1111_1111', 
         '0001.100' : '1111_1111_1111_1111', 
         '0001.011' : '1111_1111_1111_1111', 
         '0001.010' : '1111_1111_1111_1111', 
         '0001.001' : '1111_1111_1111_1111', 
         '0001.000' : '0111_1111_1111_1111', 
       
         '0000.111' : '1111_1111_1111_1111', 
         '0000.110' : '1111_1111_1111_1111', 
         '0000.101' : '1111_1111_1111_1111', 
         '0000.100' : '1111_1111_1111_1111', 
         '0000.011' : '1111_1111_1111_1111', 
         '0000.010' : '1111_1111_1111_1111', 
         '0000.001' : '1111_1111_1111_1111',
         '0000.000' : '1111_1111_1111_1111',
        
         '1111.111' : '1111_1111_1111_1111', 
         '1111.110' : '1111_1111_1111_1111', 
         '1111.101' : '1111_1111_1111_1111', 
         '1111.100' : '1111_1111_1111_1111', 
         '1111.011' : '1111_1111_1111_1111', 
         '1111.010' : '1111_1111_1111_1111', 
         '1111.001' : '1111_1111_1111_1111', 
         '1111.000' : '1111_1111_1111_1111', 
       
         '1110.111' : '1111_1111_1111_1111', 
         '1110.110' : '1111_1111_1111_1111', 
         '1110.101' : '1111_1111_1111_1111', 
         '1110.100' : '1111_1111_1111_1111', 
         '1110.011' : '1111_1111_1111_1111', 
         '1110.010' : '1111_1111_1111_1111', 
         '1110.001' : '1111_1111_1111_1111', 
         '1110.000' : '1111_1111_1111_1111', 
       
         '1101.111' : '1111_1111_1111_1111', 
         '1101.110' : '1111_1111_1111_1111', 
         '1101.101' : '1111_1111_1111_1111', 
         '1101.100' : '1111_1111_1111_1111', 
         '1101.011' : '1111_1111_1111_1111', 
         '1101.010' : '1111_1111_1111_1111', 
         '1101.001' : '1111_1111_1111_1111', 
       
         # Bottom Half - 20 entries of varying valid cells
         '1101.000' : '0111_1111_1111_1111',
        
         '1100.111' : '0011_1111_1111_1111', 
         '1100.110' : '0011_1111_1111_1111', 
         '1100.101' : '0001_1111_1111_1111', 
         '1100.100' : '0000_1111_1111_1111', 
         '1100.011' : '0000_0111_1111_1111', 
         '1100.010' : '0000_0111_1111_1111', 
         '1100.001' : '0000_0011_1111_1111', 
         '1100.000' : '0000_0001_1111_1111', 
       
         '1011.110' : '0000_0000_1111_1111', 
         '1011.101' : '0000_0000_1111_1111', 
         '1011.100' : '0000_0000_0111_1111', 
         '1011.011' : '0000_0000_0011_1111', 
         '1011.010' : '0000_0000_0001_1111', 
         '1011.001' : '0000_0000_0001_1111', 
         '1011.000' : '0000_0000_0000_1111', 
         '1011.000' : '0000_0000_0000_0111', 
       
         '1010.111' : '0000_0000_0000_0011', 
         '1010.110' : '0000_0000_0000_0011', 
         '1010.101' : '0000_0000_0000_0001', 
       }
       
       
       max_col_dec = 15
       valid_cell_addr_bins = []

       for index, row_addr in enumerate(lut_valid_entries_cell_mask):
           row_addr_bin_str     = row_addr.replace('.','') 
           valid_cell_mask_bin  = lut_valid_entries_cell_mask[row_addr].replace('_','')    
           valid_cell_mask_int  = int(valid_cell_mask_bin, 2)    
       
           for col_addr_dec in  range(0, max_col_dec+1):
              if  self.testBit(valid_cell_mask_int,  col_addr_dec):  
                 addr_bin_str   =  row_addr_bin_str +  binary_repr((max_col_dec - col_addr_dec), width=4)
                 bin_prefix_str =  'bin_' + row_addr_bin_str + '_' +  binary_repr((max_col_dec - col_addr_dec), width=4)
                 valid_cell_addr_bins.extend(self.get_custom_bin_list([str(int(addr_bin_str, 2))], bin_prefix_str))
 
       return (valid_cell_addr_bins)  



    def gen_coverage(self):
 

        # ENTRY: Built-in object to create the covergroup covering the value of signal specified when enable is true 
        with add_wbv_entry(self,
             WBV_NAME             = 'lut_2048_addr_cov',
             WBV_TYPE             = 'WBV_SIGNAL_VALUE',
             WBV_FUNCTIONAL_COV   = '1',
             WBV_CP_COV_USER      = self.get_valid_cell_addr_bins(), 
             WBV_DESCRIPTION      = 'SRT FDIV LUT organized as 128x16 matrix coverage') as wbv_entry:

            # Simplest form, Auto bins and no enable control
            wbv_entry.add_wbv_si_entry(
              SIGNAL_OR_EXPR  = '__FDIV_LUT_ADDR_11_BITS__',
              SIGNAL_ENABLE   = '__FDIV_LUT_ENABLE__') 


def main():
    curiosity_dut_cov_obj = curiosity_dut_lib() # Create the user lib for easing the wb_input entries creation

    # Setup DUT attributes  
    curiosity_dut_cov_obj.set_dut_spec(
        __DUT_CLK__                 = 'dut.clk',
        __DUT_RSTN__                = '!dut.resetn', 

        __FDIV_LUT_ADDR_11_BITS__   = 'dut.fdiv.lut_pd_2048[10:0]',
        __FDIV_LUT_ENABLE__         = 'dut.fdiv.lut_pd_2048_en',
    )  

    curiosity_dut_cov_obj.gen_coverage()


## Call the main ##

if __name__ == '__main__':
    main()

//File Name: curiosity_wb_fcov_cg.sv
//##################################################################################################################
//
//  Copyright (C) VerifSudha Technologies Pvt. Ltd.  - All Rights Reserved 2017
//  Unauthorized copying of this file, via any medium is strictly prohibited
//  Proprietary and confidential
//  Written by curiosity ,
//
//  Generated file - Donot edit manually. It will be overwritten !
//
//  File generated with the command:
//  ./curiosity -ips curiosity_ex_pentium_bug_lut_cov.py --html
//
//##################################################################################################################

covergroup lut_2048_addr_cov() @(dut.clk);
	option.comment = "SRT FDIV LUT organized as 128x16 matrix coverage";
	option.name = "lut_2048_addr_cov";
	option.per_instance = 1;

	// Cover points 
	cp_sig_val_lut_2048_addr_cov_1 : coverpoint dut.fdiv.lut_pd_2048[10:0] iff (dut.fdiv.lut_pd_2048_en){

		  bins bin_1100000_1111_value_1551 = {1551};
		  bins bin_1100000_1110_value_1550 = {1550};
		  bins bin_1100000_1101_value_1549 = {1549};
		  bins bin_1100000_1100_value_1548 = {1548};
		  bins bin_1100000_1011_value_1547 = {1547};
		  bins bin_1100000_1010_value_1546 = {1546};
		  bins bin_1100000_1001_value_1545 = {1545};
		  bins bin_1100000_1000_value_1544 = {1544};
		  bins bin_1100000_0111_value_1543 = {1543};
		  bins bin_1100001_1111_value_1567 = {1567};
		  bins bin_1100001_1110_value_1566 = {1566};
		  bins bin_1100001_1101_value_1565 = {1565};
		  bins bin_1100001_1100_value_1564 = {1564};
		  bins bin_1100001_1011_value_1563 = {1563};
		  bins bin_1100001_1010_value_1562 = {1562};
		  bins bin_1100001_1001_value_1561 = {1561};
		  bins bin_1100001_1000_value_1560 = {1560};
		  bins bin_1100001_0111_value_1559 = {1559};
		  bins bin_1100001_0110_value_1558 = {1558};
		  bins bin_1011001_1111_value_1439 = {1439};
		  bins bin_1011001_1110_value_1438 = {1438};
		  bins bin_1011001_1101_value_1437 = {1437};
		  bins bin_1011001_1100_value_1436 = {1436};
		  bins bin_1011001_1011_value_1435 = {1435};
		  bins bin_1011000_1111_value_1423 = {1423};
		  bins bin_1011000_1110_value_1422 = {1422};
		  bins bin_1011000_1101_value_1421 = {1421};
		  bins bin_0000000_1111_value_15 = {15};
		  bins bin_0000000_1110_value_14 = {14};
		  bins bin_0000000_1101_value_13 = {13};
		  bins bin_0000000_1100_value_12 = {12};
		  bins bin_0000000_1011_value_11 = {11};
		  bins bin_0000000_1010_value_10 = {10};
		  bins bin_0000000_1001_value_9 = {9};
		  bins bin_0000000_1000_value_8 = {8};
		  bins bin_0000000_0111_value_7 = {7};
		  bins bin_0000000_0110_value_6 = {6};
		  bins bin_0000000_0101_value_5 = {5};
		  bins bin_0000000_0100_value_4 = {4};
		  bins bin_0000000_0011_value_3 = {3};
		  bins bin_0000000_0010_value_2 = {2};
		  bins bin_0000000_0001_value_1 = {1};
		  bins bin_0000000_0000_value_0 = {0};
		  bins bin_0000001_1111_value_31 = {31};
		  bins bin_0000001_1110_value_30 = {30};
		  bins bin_0000001_1101_value_29 = {29};
		  bins bin_0000001_1100_value_28 = {28};
		  bins bin_0000001_1011_value_27 = {27};
		  bins bin_0000001_1010_value_26 = {26};
		  bins bin_0000001_1001_value_25 = {25};
		  bins bin_0000001_1000_value_24 = {24};
		  bins bin_0000001_0111_value_23 = {23};
		  bins bin_0000001_0110_value_22 = {22};
		  bins bin_0000001_0101_value_21 = {21};
		  bins bin_0000001_0100_value_20 = {20};
		  bins bin_0000001_0011_value_19 = {19};
		  bins bin_0000001_0010_value_18 = {18};
		  bins bin_0000001_0001_value_17 = {17};
		  bins bin_0000001_0000_value_16 = {16};
		  bins bin_0101011_1111_value_703 = {703};
		  bins bin_0101010_1111_value_687 = {687};
		  bins bin_0101010_1110_value_686 = {686};
		  bins bin_1111110_1111_value_2031 = {2031};
		  bins bin_1111110_1110_value_2030 = {2030};
		  bins bin_1111110_1101_value_2029 = {2029};
		  bins bin_1111110_1100_value_2028 = {2028};
		  bins bin_1111110_1011_value_2027 = {2027};
		  bins bin_1111110_1010_value_2026 = {2026};
		  bins bin_1111110_1001_value_2025 = {2025};
		  bins bin_1111110_1000_value_2024 = {2024};
		  bins bin_1111110_0111_value_2023 = {2023};
		  bins bin_1111110_0110_value_2022 = {2022};
		  bins bin_1111110_0101_value_2021 = {2021};
		  bins bin_1111110_0100_value_2020 = {2020};
		  bins bin_1111110_0011_value_2019 = {2019};
		  bins bin_1111110_0010_value_2018 = {2018};
		  bins bin_1111110_0001_value_2017 = {2017};
		  bins bin_1111110_0000_value_2016 = {2016};
		  bins bin_1111111_1111_value_2047 = {2047};
		  bins bin_1111111_1110_value_2046 = {2046};
		  bins bin_1111111_1101_value_2045 = {2045};
		  bins bin_1111111_1100_value_2044 = {2044};
		  bins bin_1111111_1011_value_2043 = {2043};
		  bins bin_1111111_1010_value_2042 = {2042};
		  bins bin_1111111_1001_value_2041 = {2041};
		  bins bin_1111111_1000_value_2040 = {2040};
		  bins bin_1111111_0111_value_2039 = {2039};
		  bins bin_1111111_0110_value_2038 = {2038};
		  bins bin_1111111_0101_value_2037 = {2037};
		  bins bin_1111111_0100_value_2036 = {2036};
		  bins bin_1111111_0011_value_2035 = {2035};
		  bins bin_1111111_0010_value_2034 = {2034};
		  bins bin_1111111_0001_value_2033 = {2033};
		  bins bin_1111111_0000_value_2032 = {2032};
		  bins bin_0010100_1111_value_335 = {335};
		  bins bin_0010100_1110_value_334 = {334};
		  bins bin_0010100_1101_value_333 = {333};
		  bins bin_0010100_1100_value_332 = {332};
		  bins bin_0010100_1011_value_331 = {331};
		  bins bin_0010100_1010_value_330 = {330};
		  bins bin_0010100_1001_value_329 = {329};
		  bins bin_0010100_1000_value_328 = {328};
		  bins bin_0010100_0111_value_327 = {327};
		  bins bin_0010100_0110_value_326 = {326};
		  bins bin_0010100_0101_value_325 = {325};
		  bins bin_0010100_0100_value_324 = {324};
		  bins bin_0010100_0011_value_323 = {323};
		  bins bin_0010100_0010_value_322 = {322};
		  bins bin_0010100_0001_value_321 = {321};
		  bins bin_0010100_0000_value_320 = {320};
		  bins bin_0010101_1111_value_351 = {351};
		  bins bin_0010101_1110_value_350 = {350};
		  bins bin_0010101_1101_value_349 = {349};
		  bins bin_0010101_1100_value_348 = {348};
		  bins bin_0010101_1011_value_347 = {347};
		  bins bin_0010101_1010_value_346 = {346};
		  bins bin_0010101_1001_value_345 = {345};
		  bins bin_0010101_1000_value_344 = {344};
		  bins bin_0010101_0111_value_343 = {343};
		  bins bin_0010101_0110_value_342 = {342};
		  bins bin_0010101_0101_value_341 = {341};
		  bins bin_0010101_0100_value_340 = {340};
		  bins bin_0010101_0011_value_339 = {339};
		  bins bin_0010101_0010_value_338 = {338};
		  bins bin_0010101_0001_value_337 = {337};
		  bins bin_0010101_0000_value_336 = {336};
		  bins bin_0001100_1111_value_207 = {207};
		  bins bin_0001100_1110_value_206 = {206};
		  bins bin_0001100_1101_value_205 = {205};
		  bins bin_0001100_1100_value_204 = {204};
		  bins bin_0001100_1011_value_203 = {203};
		  bins bin_0001100_1010_value_202 = {202};
		  bins bin_0001100_1001_value_201 = {201};
		  bins bin_0001100_1000_value_200 = {200};
		  bins bin_0001100_0111_value_199 = {199};
		  bins bin_0001100_0110_value_198 = {198};
		  bins bin_0001100_0101_value_197 = {197};
		  bins bin_0001100_0100_value_196 = {196};
		  bins bin_0001100_0011_value_195 = {195};
		  bins bin_0001100_0010_value_194 = {194};
		  bins bin_0001100_0001_value_193 = {193};
		  bins bin_0001100_0000_value_192 = {192};
		  bins bin_0001101_1111_value_223 = {223};
		  bins bin_0001101_1110_value_222 = {222};
		  bins bin_0001101_1101_value_221 = {221};
		  bins bin_0001101_1100_value_220 = {220};
		  bins bin_0001101_1011_value_219 = {219};
		  bins bin_0001101_1010_value_218 = {218};
		  bins bin_0001101_1001_value_217 = {217};
		  bins bin_0001101_1000_value_216 = {216};
		  bins bin_0001101_0111_value_215 = {215};
		  bins bin_0001101_0110_value_214 = {214};
		  bins bin_0001101_0101_value_213 = {213};
		  bins bin_0001101_0100_value_212 = {212};
		  bins bin_0001101_0011_value_211 = {211};
		  bins bin_0001101_0010_value_210 = {210};
		  bins bin_0001101_0001_value_209 = {209};
		  bins bin_0001101_0000_value_208 = {208};
		  bins bin_1100011_1111_value_1599 = {1599};
		  bins bin_1100011_1110_value_1598 = {1598};
		  bins bin_1100011_1101_value_1597 = {1597};
		  bins bin_1100011_1100_value_1596 = {1596};
		  bins bin_1100011_1011_value_1595 = {1595};
		  bins bin_1100011_1010_value_1594 = {1594};
		  bins bin_1100011_1001_value_1593 = {1593};
		  bins bin_1100011_1000_value_1592 = {1592};
		  bins bin_1100011_0111_value_1591 = {1591};
		  bins bin_1100011_0110_value_1590 = {1590};
		  bins bin_1100011_0101_value_1589 = {1589};
		  bins bin_1100010_1111_value_1583 = {1583};
		  bins bin_1100010_1110_value_1582 = {1582};
		  bins bin_1100010_1101_value_1581 = {1581};
		  bins bin_1100010_1100_value_1580 = {1580};
		  bins bin_1100010_1011_value_1579 = {1579};
		  bins bin_1100010_1010_value_1578 = {1578};
		  bins bin_1100010_1001_value_1577 = {1577};
		  bins bin_1100010_1000_value_1576 = {1576};
		  bins bin_1100010_0111_value_1575 = {1575};
		  bins bin_1100010_0110_value_1574 = {1574};
		  bins bin_1100010_0101_value_1573 = {1573};
		  bins bin_0100100_1111_value_591 = {591};
		  bins bin_0100100_1110_value_590 = {590};
		  bins bin_0100100_1101_value_589 = {589};
		  bins bin_0100100_1100_value_588 = {588};
		  bins bin_0100100_1011_value_587 = {587};
		  bins bin_0100100_1010_value_586 = {586};
		  bins bin_0100101_1111_value_607 = {607};
		  bins bin_0100101_1110_value_606 = {606};
		  bins bin_0100101_1101_value_605 = {605};
		  bins bin_0100101_1100_value_604 = {604};
		  bins bin_0100101_1011_value_603 = {603};
		  bins bin_0000011_1111_value_63 = {63};
		  bins bin_0000011_1110_value_62 = {62};
		  bins bin_0000011_1101_value_61 = {61};
		  bins bin_0000011_1100_value_60 = {60};
		  bins bin_0000011_1011_value_59 = {59};
		  bins bin_0000011_1010_value_58 = {58};
		  bins bin_0000011_1001_value_57 = {57};
		  bins bin_0000011_1000_value_56 = {56};
		  bins bin_0000011_0111_value_55 = {55};
		  bins bin_0000011_0110_value_54 = {54};
		  bins bin_0000011_0101_value_53 = {53};
		  bins bin_0000011_0100_value_52 = {52};
		  bins bin_0000011_0011_value_51 = {51};
		  bins bin_0000011_0010_value_50 = {50};
		  bins bin_0000011_0001_value_49 = {49};
		  bins bin_0000011_0000_value_48 = {48};
		  bins bin_0000010_1111_value_47 = {47};
		  bins bin_0000010_1110_value_46 = {46};
		  bins bin_0000010_1101_value_45 = {45};
		  bins bin_0000010_1100_value_44 = {44};
		  bins bin_0000010_1011_value_43 = {43};
		  bins bin_0000010_1010_value_42 = {42};
		  bins bin_0000010_1001_value_41 = {41};
		  bins bin_0000010_1000_value_40 = {40};
		  bins bin_0000010_0111_value_39 = {39};
		  bins bin_0000010_0110_value_38 = {38};
		  bins bin_0000010_0101_value_37 = {37};
		  bins bin_0000010_0100_value_36 = {36};
		  bins bin_0000010_0011_value_35 = {35};
		  bins bin_0000010_0010_value_34 = {34};
		  bins bin_0000010_0001_value_33 = {33};
		  bins bin_0000010_0000_value_32 = {32};
		  bins bin_1111101_1111_value_2015 = {2015};
		  bins bin_1111101_1110_value_2014 = {2014};
		  bins bin_1111101_1101_value_2013 = {2013};
		  bins bin_1111101_1100_value_2012 = {2012};
		  bins bin_1111101_1011_value_2011 = {2011};
		  bins bin_1111101_1010_value_2010 = {2010};
		  bins bin_1111101_1001_value_2009 = {2009};
		  bins bin_1111101_1000_value_2008 = {2008};
		  bins bin_1111101_0111_value_2007 = {2007};
		  bins bin_1111101_0110_value_2006 = {2006};
		  bins bin_1111101_0101_value_2005 = {2005};
		  bins bin_1111101_0100_value_2004 = {2004};
		  bins bin_1111101_0011_value_2003 = {2003};
		  bins bin_1111101_0010_value_2002 = {2002};
		  bins bin_1111101_0001_value_2001 = {2001};
		  bins bin_1111101_0000_value_2000 = {2000};
		  bins bin_1111100_1111_value_1999 = {1999};
		  bins bin_1111100_1110_value_1998 = {1998};
		  bins bin_1111100_1101_value_1997 = {1997};
		  bins bin_1111100_1100_value_1996 = {1996};
		  bins bin_1111100_1011_value_1995 = {1995};
		  bins bin_1111100_1010_value_1994 = {1994};
		  bins bin_1111100_1001_value_1993 = {1993};
		  bins bin_1111100_1000_value_1992 = {1992};
		  bins bin_1111100_0111_value_1991 = {1991};
		  bins bin_1111100_0110_value_1990 = {1990};
		  bins bin_1111100_0101_value_1989 = {1989};
		  bins bin_1111100_0100_value_1988 = {1988};
		  bins bin_1111100_0011_value_1987 = {1987};
		  bins bin_1111100_0010_value_1986 = {1986};
		  bins bin_1111100_0001_value_1985 = {1985};
		  bins bin_1111100_0000_value_1984 = {1984};
		  bins bin_0001111_1111_value_255 = {255};
		  bins bin_0001111_1110_value_254 = {254};
		  bins bin_0001111_1101_value_253 = {253};
		  bins bin_0001111_1100_value_252 = {252};
		  bins bin_0001111_1011_value_251 = {251};
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		  bins bin_0001111_1001_value_249 = {249};
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		  bins bin_0100111_1100_value_636 = {636};
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		  bins bin_0100110_1101_value_621 = {621};
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		  bins bin_1101000_1111_value_1679 = {1679};
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		  bins bin_1011110_1101_value_1517 = {1517};
		  bins bin_1011110_1100_value_1516 = {1516};
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		  bins bin_1010110_1111_value_1391 = {1391};
		  bins bin_1010110_1110_value_1390 = {1390};
		  bins bin_1010111_1111_value_1407 = {1407};
		  bins bin_1010111_1110_value_1406 = {1406};
		  bins bin_1111000_1111_value_1935 = {1935};
		  bins bin_1111000_1110_value_1934 = {1934};
		  bins bin_1111000_1101_value_1933 = {1933};
		  bins bin_1111000_1100_value_1932 = {1932};
		  bins bin_1111000_1011_value_1931 = {1931};
		  bins bin_1111000_1010_value_1930 = {1930};
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		  bins bin_1111000_0011_value_1923 = {1923};
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		  bins bin_1111000_0001_value_1921 = {1921};
		  bins bin_1111000_0000_value_1920 = {1920};
		  bins bin_1111001_1111_value_1951 = {1951};
		  bins bin_1111001_1110_value_1950 = {1950};
		  bins bin_1111001_1101_value_1949 = {1949};
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		  bins bin_1111001_1011_value_1947 = {1947};
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		  bins bin_1110001_0011_value_1811 = {1811};
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		  bins bin_1110001_0001_value_1809 = {1809};
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		  bins bin_1111011_1111_value_1983 = {1983};
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		  bins bin_1111011_1101_value_1981 = {1981};
		  bins bin_1111011_1100_value_1980 = {1980};
		  bins bin_1111011_1011_value_1979 = {1979};
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		  bins bin_1111011_0100_value_1972 = {1972};
		  bins bin_1111011_0011_value_1971 = {1971};
		  bins bin_1111011_0010_value_1970 = {1970};
		  bins bin_1111011_0001_value_1969 = {1969};
		  bins bin_1111011_0000_value_1968 = {1968};
		  bins bin_1111010_1111_value_1967 = {1967};
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		  bins bin_1111010_1101_value_1965 = {1965};
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		  bins bin_0001000_1110_value_142 = {142};
		  bins bin_0001000_1101_value_141 = {141};
		  bins bin_0001000_1100_value_140 = {140};
		  bins bin_0001000_1011_value_139 = {139};
		  bins bin_0001000_1010_value_138 = {138};
		  bins bin_0001000_1001_value_137 = {137};
		  bins bin_0001000_1000_value_136 = {136};
		  bins bin_0001000_0111_value_135 = {135};
		  bins bin_0001000_0110_value_134 = {134};
		  bins bin_0001000_0101_value_133 = {133};
		  bins bin_0001000_0100_value_132 = {132};
		  bins bin_0001000_0011_value_131 = {131};
		  bins bin_0001000_0010_value_130 = {130};
		  bins bin_0001000_0001_value_129 = {129};
		  bins bin_0100001_1111_value_543 = {543};
		  bins bin_0100001_1110_value_542 = {542};
		  bins bin_0100001_1101_value_541 = {541};
		  bins bin_0100001_1100_value_540 = {540};
		  bins bin_0100001_1011_value_539 = {539};
		  bins bin_0100001_1010_value_538 = {538};
		  bins bin_0100001_1001_value_537 = {537};
		  bins bin_0100001_1000_value_536 = {536};
		  bins bin_0100000_1111_value_527 = {527};
		  bins bin_0100000_1110_value_526 = {526};
		  bins bin_0100000_1101_value_525 = {525};
		  bins bin_0100000_1100_value_524 = {524};
		  bins bin_0100000_1011_value_523 = {523};
		  bins bin_0100000_1010_value_522 = {522};
		  bins bin_0100000_1001_value_521 = {521};
		  bins bin_0100000_1000_value_520 = {520};
		  bins bin_0100000_0111_value_519 = {519};
		  bins bin_1011010_1111_value_1455 = {1455};
		  bins bin_1011010_1110_value_1454 = {1454};
		  bins bin_1011010_1101_value_1453 = {1453};
		  bins bin_1011010_1100_value_1452 = {1452};
		  bins bin_1011010_1011_value_1451 = {1451};
		  bins bin_1011011_1111_value_1471 = {1471};
		  bins bin_1011011_1110_value_1470 = {1470};
		  bins bin_1011011_1101_value_1469 = {1469};
		  bins bin_1011011_1100_value_1468 = {1468};
		  bins bin_1011011_1011_value_1467 = {1467};
		  bins bin_1011011_1010_value_1466 = {1466};
		  bins bin_0101000_1111_value_655 = {655};
		  bins bin_0101000_1110_value_654 = {654};
		  bins bin_0101000_1101_value_653 = {653};
		  bins bin_0101001_1111_value_671 = {671};
		  bins bin_0101001_1110_value_670 = {670};
		  bins bin_1110111_1111_value_1919 = {1919};
		  bins bin_1110111_1110_value_1918 = {1918};
		  bins bin_1110111_1101_value_1917 = {1917};
		  bins bin_1110111_1100_value_1916 = {1916};
		  bins bin_1110111_1011_value_1915 = {1915};
		  bins bin_1110111_1010_value_1914 = {1914};
		  bins bin_1110111_1001_value_1913 = {1913};
		  bins bin_1110111_1000_value_1912 = {1912};
		  bins bin_1110111_0111_value_1911 = {1911};
		  bins bin_1110111_0110_value_1910 = {1910};
		  bins bin_1110111_0101_value_1909 = {1909};
		  bins bin_1110111_0100_value_1908 = {1908};
		  bins bin_1110111_0011_value_1907 = {1907};
		  bins bin_1110111_0010_value_1906 = {1906};
		  bins bin_1110111_0001_value_1905 = {1905};
		  bins bin_1110111_0000_value_1904 = {1904};
		  bins bin_1110110_1111_value_1903 = {1903};
		  bins bin_1110110_1110_value_1902 = {1902};
		  bins bin_1110110_1101_value_1901 = {1901};
		  bins bin_1110110_1100_value_1900 = {1900};
		  bins bin_1110110_1011_value_1899 = {1899};
		  bins bin_1110110_1010_value_1898 = {1898};
		  bins bin_1110110_1001_value_1897 = {1897};
		  bins bin_1110110_1000_value_1896 = {1896};
		  bins bin_1110110_0111_value_1895 = {1895};
		  bins bin_1110110_0110_value_1894 = {1894};
		  bins bin_1110110_0101_value_1893 = {1893};
		  bins bin_1110110_0100_value_1892 = {1892};
		  bins bin_1110110_0011_value_1891 = {1891};
		  bins bin_1110110_0010_value_1890 = {1890};
		  bins bin_1110110_0001_value_1889 = {1889};
		  bins bin_1110110_0000_value_1888 = {1888};
	}

	// Cross coverage 

endgroup : lut_2048_addr_cov

Out of these 1066 cells following 5 cells were left uninitialized in this famous bug. Row and columns of address of uninitialized cells were following. You can spot them in generated functional coverage code.

0101000_1101
0100100_1010
0100000_0111
0011100_0100
0011000_0001

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