Why Silicon proven IPs are treated special?

Silicon proven IPs do enjoy some special attention to envy of the one’s aren’t. Do they really deserve it? What is so special about them?

Simulation however much we love and adore is simulation. It’s not real. There are lots of aspects not modeled in the simulation. We may take lot of pride in our latest verification simulation technologies, but still there are lots of details of real world that IPs get shielded in simulation environment. Lets call them simulation blind spots.

Those blind spots can be categorized into into three major areas:

• Electrical characteristics of physical communication channels
• Quirks of analog parts of the design
• Software application interactions

Even beyond all these simulation has speed challenge. For larger designs the highest simulation time is limited by the highest tolerable wall clock times.

Though there are technologies in development to manage these problems independently and in some combinations but there isn’t one clean solution that fits all. Current verification strategy is still work in progress to address these blind spots.

Silicon is real world where all of it comes together. If the design IPs were to be real person, it would be very stressful for them to handle all of these together. That’s why many fail.

First time silicon is like “meet the parents” moment for design IP. The design IP that hasn’t had this moment is still not in the circle of trust. There are many jinx moments for them.

Why are these blind spots such a big deal?

Simple power on reset value for physical pad being incorrect can potentially leave a particular interface dead. Eye of signal can be real eye openers.

Suddenly the clock tolerance of 4 % becomes highly meaningful when the input sampling of the signal starts failing to detect the right data.

That status register which we never cared about becomes hero overnight when software polls that register to figure out why commands are failing.

Crazy things happen in real world. Suddenly those streams of all 0s and all 1s for few milliseconds may seem like cyclone. That line in specification, which almost looked so harmless isn’t harmless any more when you start seeing the wake signals being beaconed at not so good time for your design. That clock gating and wake coming together is not so pleasant.

That’s exactly the reasons why  silicon experience and exposure to real world for design IPs does earn them special place over the ones that aren’t silicon proven.