Verification quality improvement – Legacy test benches

Legacy tests benches are the ones based on the hardware description language(HDL)s like VHDL or Verilog, with or without high level languages such as C or C++. These test benches are not based on the coverage driven constrained random approach. Although they may also contain randomization approach in rudimentary form.

Typically designed for the early first generation of the older designs. It would have provided the necessary coverage at that point but as newer revisions show up with the increased complexity the legacy technologies based test bench may not be able to do a good job.

In fact beyond certain point of design complexity the effort to verify the feature in the legacy test bench for the same coverage can become significantly higher compared to latest HVL and verification methodology driven test benches. This is because of lack of built-in support for the constructs aiding the constrained random verification. Finding engineers to maintain and update the legacy test benches can also become challenging.

Key question for functional verification quality overhaul of legacy test benches are following.

How to go about quality overhaul of legacy HDL based test benches?

Although case by case it can vary but if you do plan to use the design for next three years and you see the possibility of significant updates taking place to design its better to start planning to move to latest technologies.

However that is easier said than done but quicker migration will help you derive more value from your investments. So if you are seeing serious quality problems with the legacy test benches it’s better to start phasing them out.

Don’t take middle level path of salvaging parts from legacy HDL based test bench verification components to build the new HVL based test bench. It may backfire.

If you want to extend the life of the legacy HDL based test bench consider adding some of HVL based features into the same test bench. For example adding functional coverage can be first step towards HVL adoption. Subsequently configuration randomization can be added. Newer stimulus generation requirements can be handled in the HVL and leaving the rest of the design interaction to the legacy test bench components. But please don’t design a brand new HVL based test bench around salvaging the older verification components.

How to go about quality overhaul of older HVLs such as Specman e or VERA based test benches?

It should be possible to refactor them where needed to get them in shape. Justifying the value of migration to new HVLs might be hard if not impossible. Although migrating to latest and greatest for designs that survive longer pays back for itself.

How to go about quality overhaul of older verification methodologies such as VMM and OVM?

It should be possible to continue to use them. Switching from VMM to UVM can prove to be quite challenging as there are philosophical differences between the methodologies. It may be better to stay with the VMM.

While OVM to UVM switch could be handled through partly by automation and partly through manual effort. For design’s to be maintained long term, this migration makes sense to get the benefits of the UVM.